When you hear “processor architecture,” what are the first things that come to mind? Most likely, x86 and ARM. But now there is a new player in town — RISC-V. What is it? How does it differ from ARM? How did it manage to evolve from a project created by a group of university researchers into a thriving platform supported by such tech giants as Google, Alibaba, Huawei, and even Intel? And is there a Java port? Find the answers in our article!
Table of Contents
RISC-V architecture and history
RISC-V (pronounced as “risc-five”) is an open-source instruction set architecture (ISA) based on the reduced instruction set computer (RISC) model. ISA is an abstract computer model, which defines basic operations and describes how to use them, i.e., instructions. These instructions act as a communication bridge between hardware and software. RISC-V includes 47 base instructions, and additional extensions can be added in a modular way.
The RISC-V project was created in 2010 at the University of California, Berkeley, by a group of engineers led by Krste Asanović and David Patterson. In 2015, the RISC-V Foundation was founded to stimulate the interest in RISC-V among commercial users, and the project authors transferred their rights to the Foundation. The RISC-V Foundation was later renamed RISC-V International. The project rapidly gained popularity among researchers and IT companies all over the world, and now the nonprofit organization has more than 2,000 members and such partners as Google, IBM, NVIDIA, Western Digital, etc. In 2018, the organization declared a collaboration with the Linux Foundation. But the absolute highlight happened in 2022, when Intel joined RISC-V International and announced that it is investing $1 billion in the RISC-V ecosystem, the biggest expenditure on the project so far.
So what is the secret behind RISC-V’s success? What are the prerequisites for its brilliant future? Let’s find out!
What makes RISC-V good
RISC vs CISC
To understand what makes RISC-V a revolutionary technology, it should first be noted that initially, there were two types of microprocessor design: RISC and CISC (complex instruction set computer). In CISC, one instruction set executes several low-level operations (loading, evaluation, data storage). Hence, a program uses fewer specialized instructions, but the number of cycles per instruction is higher. A typical example of CISC architecture is x86. RISC, on the other hand, uses a smaller customized set of instructions, so each program will utilize several instructions, but each instruction is executed on one clock cycle. The execution of several one-cycle instructions takes less time thus enhancing the CPU performance. In addition, pipelining with RISC is more efficient because the initial idea was that each instruction needs equal time to execute. This is not the case for the complex instructions, but the original strategy is implemented in simple hardware. Finally, developing RISC processors is easier and less expensive thanks to a simple instruction set and smaller chips.
Pure RISC and CISC architectures are a thing of the past. Right now, all architectures are RISC-like, even x86, which decodes CISC into RISC-like micro-operations.
Open-source nature of RISC-V
The difference between CISC and RISC is clear, but what exactly is RISC-V? Is it just a fancy name for RISC? Not exactly. RISC-V is an open and free architecture model. It has all the advantages of RISC enhanced by its open-source nature:
- It is modular, hence flexible. Developers use modules to create any type of device, from compact embedded systems to powerful computers.
- It boosts innovation. There’s no need to pay royalties for using RISC-V design in research and development, which makes it possible for any enthusiast to contribute to its improvement.
- It reduces costs of development and speeds up time-to-market. The reuse of open-source intellectual property (IP) enables fast and cost-effective development of software and hardware.
- There is no single commercial company that rules RISC-V development and production, as opposed to x86, where Intel is almost a monopoly. RISC-V International is an NGO that unites various companies committed to the improvement of this microprocessor architecture.
RISC-V adoption across industries
According to the RISC-V Market Analysis conducted by Semico, the annual growth rate of RISC-V cores will reach 160% and capture a >14% (approx. 80 billion CPU cores) share of the semiconductor market by 2025. RISC-V advancement is gaining momentum as these processors get adopted by more industries every year. Thanks to their flexibility, high performance, and scalability, they can now be found in any type of device and category, including:
- Internet of Things
- Automotive
- Machine learning and artificial intelligence
- Telecom
- Cloud servers and data centers
- Edge computing
- Personal computers, supercomputers, microcontrollers
This list proves that RISC-V is a working alternative to ARM and x86 proprietary solutions.
What is more, RISC-V International provides all kinds of support to its members: online learning, university labs, compatibility suites and tests, events for developers and industry players, as well as an online marketplace. In addition, boards for developing RISC-V applications have become widely available, for example, SiFive Board.
Furthermore, the RISC-V Software Ecosystem (RISE) project was founded by industry leaders to complement the efforts of RISC-V International and accelerate the development of software for RISC-V.
So RISC-V is not just architecture. It is a thriving ecosystem, which is predicted to shape the following decades of computing innovation by means of open cooperation.
RISC-V vs ARM
Both RISC-V and ARM are based on the RISC architecture model as opposed to x86. To note: there is also AArch64, a 64-bit extension of ARM architecture since ARMv8-A. Although ARM still holds a dominant position in the RISC market, it faces serious competition from RISC-V. The table below outlines the major differences between the two.
| ARM | RISC-V | |
|---|---|---|
| Business model | ARM is based on a proprietary IP model, which means that you have to pay royalties to integrate an ARM processor into your device. | RISC-V is open-source and free, so anyone can use it for research and development without paying royalties or violating any patents. |
| Ecosystem | As ARM has been around since the 1980s, it has a large community, a lot of libraries, and supports a wide range of software. | RISC-V is a relatively new technology, but its community and technical support is rapidly growing. |
| Power consumption | According to the tests, the average ARM power consumption is around 36.8 milliWatts. | The same tests show that in specific cases, RISC-V consumes three times less power than ARM. |
| Customization | ARM has recently started integrating standardized instructions for custom coprocessors, i.e. the instruction set is defined but its implementations may be adjusted. This is similar to how Java interfaces work. | RISC-V includes a set of basic instructions and enables engineers to use standardized or custom extensions they need for their design. |
In summary, the key difference between ARM and RISC-V is the business model. The open-source approach to RISC-V development opens the door to experiments, innovation, and rapid improvement.
RISC-V and Java
BellSoft, as a major contributor to OpenJDK, welcomes all things open-source. This approach has already proven itself with Java by making it one of the most popular, secure, and rapidly evolving programming languages. We predict a similar future for RISC-V. The OpenJDK community shares our optimism, and its members have been working on the Java port to Linux/RISC-V within the RISC-V Project. The port was integrated into JDK 19 (JEP422). Huawei was the author of the port, which was completed and published in their repository in May 2021, and then became the basis of the current RISC-V project.
The port currently supports the general-purpose 64-bit RISC-V configuration (RV64GV). This configuration includes useful instruction sets for Java types implementation: vector operations, floating-point arithmetic operations, atomic operations, base integer instruction sets, etc. Several HotSpot subsystems are also included:
- The template interpreter
- The C1 (server) JIT compiler
- The C2 (client) JIT compiler
- All current mainline Garbage Collectors, including ZGC and Shenandoah
Moreover, experimental support was added for the following extensions: RVV, RVC, Zba, and Zbb. They need to be explicitly enabled in JVM through the following options:
-XX:+UseRVV-XX:+UseRVC-XX:+UseZba-XX:+UseZbb
The Java port is a valuable addition to both ecosystems because the range of RISC-V hardware is rapidly increasing, and there is a high demand for software support. In addition, all OpenJDK vendors will take part in porting future Java changes to this ISA model.
BellSoft goes even further as far as the Java and RISC-V friendship is concerned. We have a special version of our Java runtime, Liberica JDK for Embedded, which is currently optimized for embedded systems working on ARM32 and ARM64. As RISC-V is widely used in embedded devices, we are planning to add the support for this microprocessor architecture, and both platforms will become a powerful development combo.
Conclusion
As it turns out, RISC-V and Java have a lot in common. They are both open-source, aimed at platform independence, free, and help to avoid vendor lock-in. In addition, they have a community committed to constant innovation through collaboration. So we might expect that this combo will bear very interesting and powerful solutions in the future.
